FIG. 1A is a schematic cross-sectional view illustrating a memory cell of a conventional non-volatile memory. FIG. 1B is a circuit diagram illustrating an equivalent circuit of the memory cell of FIG. 1A. Each memory cell of the conventional non-volatile memory comprises three serially-connected n-type transistors M1, M2 and M3, which are constructed in a p-well region PW. Moreover, the memory cell is separated from the adjacent memory cells through shallow trench isolation (STI) structures 102 and 104.
A first n-type doped region 112, a second n-type doped region 114, a third n-type doped region 116 and a fourth n-type doped region 118 are formed in the p-well region PW. A first gate 122 is spanned over the first n-type doped region 112 and the second n-type doped region 114. A second gate 124 is spanned over the second n-type doped region 114 and the third n-type doped region 116. A third gate 126 is spanned over the third n-type doped region 116 and the fourth n-type doped region 118.
The first n-type transistor M1 is a select transistor. The first gate 122 of the first n-type transistor M1 is connected with a first word line WL1. The first n-type doped region 112 is connected with a bit line BL. The second n-type doped region 114 is a combination of the n-type doped region of the first n-type transistor M1 and the n-type doped region of the second n-type transistor M2.
The second n-type transistor M2 is a floating gate transistor. The second gate 124 of the second n-type transistor M2 is a floating gate. A capacitor C is connected between a control line CL and the floating gate. The third n-type doped region 116 is a combination of the n-type doped region of the second n-type transistor M2 and the n-type doped region of the third n-type transistor M3.
The third n-type transistor M3 is a select transistor. The third gate 126 is connected with a second word line WL2. The fourth n-type doped region 118 is connected with a source line SL.
FIG. 2 schematically illustrates associated bias voltages for programming the conventional non-volatile memory.
Before the program action on the memory cell is performed, a first word line voltage Vw1 provided to the first word line WL1 is 3.3V, a second word line voltage Vw2 provided to the second word line WL2 is 3.3V, a control line voltage Vc provided to the control line CL is 3.3V, a bit line voltage Vb provided to the bit line BL is 0V, a source line voltage Vs provided to the source line SL is 0V, and the p-well region PW receives a ground voltage (0V). Meanwhile, the first n-type transistor M1 and the third n-type transistor M3 are turned on. Consequently, the voltages of the n-type doped regions 112, 114, 116 and 118 are all 0V.
Please refer to FIG. 2. When the program action on the memory cell is started, only the control line voltage Vc is increased to 10V and the voltages at the other terminals are kept unchanged. Meanwhile, the voltage difference between the control line voltage Vc and the two n-type doped regions 114 and 116 is about 10V. Consequently, a gate oxide layer of the second n-type transistor M2 (i.e., the floating gate transistor) results in a Fowler-Nordheim tunneling effect (i.e., the FN tunneling effect), and the carriers are injected from a channel region of the second n-type transistor M2 into the second gate 124. After the memory cell is programmed, the carrier is stored in the floating gate of the floating gate transistor. The carriers are electrons.
FIG. 3A schematically illustrates associated bias voltages for performing a program inhibition on the conventional non-volatile memory. FIG. 3B schematically illustrates the voltage change of the n-doped region of the memory cell of the conventional non-volatile memory.
Before the program inhibition is performed on the memory cell, the first word line voltage Vw1 provided to the first word line WL1, the second word line voltage Vw2 provided to the second word line WL2, the control line voltage Vc provided to the control line CL, the bit line voltage Vb provided to the bit line BL and the source line voltage Vs provided to the source line SL are all 3.3V, and the p-well region PW receives a ground voltage (0V). Meanwhile, the first n-type transistor M1 and the third n-type transistor M3 are turned off. Consequently, the voltages applied to the n-type doped regions 112 and 118 are 3.3V. Moreover, the n-type doped regions 114 and 116 are in a floating state, and the voltages of the n-type doped regions 114 and 116 are equal to (3.3V−Vth), wherein Vth is a threshold voltage of the select transistors M1 and M3.
Please refer to FIG. 3A. When the program inhibition on the memory cell is started, only the control line voltage Vc is increased to 10V and the voltages at the other terminals are kept unchanged. Since the n-type doped regions 114 and 116 are in the floating state, the voltages of the n-type doped regions 114 and 116 are boosted from (3.3V−Vth) to a boost voltage. The boost voltage is slightly lower than Vc. For example, the boost voltage is about 8.5V. Meanwhile, the voltage difference between the control line voltage Vc and the two n-type doped regions 114 and 116 is 1.5V. Consequently, the gate oxide layer of the second n-type transistor M2 (i.e., the floating gate transistor) does not result in the FN tunneling effect, and no carriers are injected into the floating gate.
Moreover, the voltages provided to the n-type doped regions 112, 114, 116 and 118 are positive voltages, and the voltage provided to the p-well region PW is 0V. Consequently, a depletion region 132 is formed between these n-type doped regions and the p-well region PW. Moreover, a drain-gate voltage Vdg (e.g., 8.5V−3.3V) between the first gate 122 and the second n-type doped region 114 of the first n-type transistor M1 results in a gate-induced drain leakage (GIDL) current i1. Similarly, a drain-gate voltage Vdg between the third gate 126 and the third n-type doped region 116 of the third n-type transistor M3 results in a GIDL current i2. Because of the GIDL current i1 and the GIDL current i2, the boost voltages of the n-type doped regions 114 and 116 decrease.
Please refer to FIG. 3B. At the time point ta, the control line voltage Vc is increased to 10V. Consequently, the voltages of the n-type doped regions 114 and 116 are increased to 8.5V. Because of the GIDL current i1 and the GIDL current i2, the voltages of the n-type doped regions 114 and 116 are decreased from 8.5V. Accordingly, the voltage difference ΔV between the control line voltage Vc and the n-type doped regions 114 and 116 is gradually increased. If the voltage difference ΔV is too large, the second n-type transistor M2 (i.e., the floating gate transistor) possibly results in the FN tunneling effect. Under this circumstance, the memory cell is erroneously programmed.
As mentioned above, the memory cell is adversely affected by the GIDL current i1 and the GIDL current i2 while the program inhibition is performed. In other words, the possibility of erroneously programming the memory cell is increased.